Hi, I'm
Undergraduate researcher in AI hardware — computer architecture, VLSI, and efficient, deterministic machine learning, from circuits to compilers.
About
I'm a final-year B.Tech student in Electrical & Computer Engineering at Shiv Nadar Institution of Eminence, working at the intersection of hardware and AI — in both directions.
On the hardware-for-AI side: accelerator architectures, memory systems, and making large-model inference efficient, adaptive and reproducible on real hardware. On the AI-for-hardware side, I spent summer 2026 at STMicroelectronics building automation for memory design — a generator that emits synthesis-ready ECC RTL, the verification harness that proves it correct, and a controlled study of what LLMs can and cannot contribute to RTL generation.
My undergraduate thesis is an open-source GPU microarchitecture designed from first principles — ISA, microarchitecture and synthesizable RTL, patent-unencumbered — because this field shouldn't stay locked behind a handful of proprietary architectures. The golden-model simulator came first, so the RTL can be checked against something known-correct rather than debugged in isolation.
I'm applying to PhD programmes for Fall 2027. I'd like to spend it on the architectures and memory systems that will run the next generation of models, and on the methodology question underneath my current work: how do you know a hardware result is real?
Research interests
Publications
6 papers · 5 as first author
No papers match that filter.
Bitwise-Reproducible Reduction Across Cluster Reshape: A Compiler/Fabric ABI.
RMAI: Runtime Multi-Objective Adaptive Inference through Joint Dynamic Sparsity and Precision Scaling on Resource-Constrained IoT Edge Devices.
Learn the Interface, Not the Implementation: Output Representation Dominates Training Regime in LLM-Based RTL Generation.
Projects
A fully open, patent-unencumbered GPU built from first principles — microarchitecture, ISA, and synthesizable RTL. Existing GPU designs are locked behind AMD/NVIDIA IP; this is an attempt to build a credible, teachable alternative in the open. This is my undergraduate thesis.
A framework that jointly tunes per-layer sparsity and quantization to live device state (thermal, power, load) on resource-constrained edge hardware — trading accuracy for efficiency only when conditions demand it.
14.8% lower latency · 15.4% energy savings vs static INT8 (ResNet-50, Raspberry Pi 4)
A compiler/fabric ABI that guarantees bit-identical reduction results across heterogeneous GPU cluster reshapes — so a run is reproducible even when the cluster topology underneath it changes.
A Python generator that replaces a manual, per-variant RTL flow with synthesis-ready SEC/SECDED ECC memory RTL, the verification harness around it, and a controlled study of what LLMs can and cannot contribute to RTL generation.
More experiments and code live on GitHub (@thesid16) .
Experience
STMicroelectronics · Greater Noida, India
Department of Electrical Engineering, Shiv Nadar Institution of Eminence · Greater Noida, India
Department of Electrical Engineering, Shiv Nadar Institution of Eminence · Greater Noida, India
Electronics manufacturer (confidential) · Delhi NCR, India
Honors
Shiv Nadar Institution of Eminence
University-wide recipient, Class of 2027.
IEEE ICNARI 2026
IEEE International Conference on Next-Generation Adaptive Research & Innovations.
Anveshana National Science Fair · 2025
Selected from 20,000+ applicants nationwide.
Life Link health platform · 2024–25
INR 100K grant with mentorship and incubation support.
School of Engineering
For academic standing — Fall 2023, Spring 2024, Fall 2025, and Spring 2026.
CGPA 8.75 / 10
Consistent academic standing in Electrical & Computer Engineering.
Service
IEEE ICNARI 2026
IEEE International Conference on Next-Generation Adaptive Research & Innovations (ICNARI).
Anveshana National Science Fair · Pragati Maidan, Delhi · 2024–25
Led workshops for 50+ school students and presented a secure-IoT prototype to 300+ attendees.
